Researchers to Examine Heat Dissipation in Three-Dimensional Integrated Circuits

January 18th, 2013

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A team of UT Arlington researchers funded by the National Science Foundation has been formed to examine potential solutions for heat minimization and dissipation in three-dimensional integrated circuits.

According to Ankur Jain, assistant professor of mechanical and aerospace engineering at UT Arlington and a member of the research team, the limited amount of available space on an integrated circuits has forced engineers to “build vertically, placing wafers on top of wafers.”

Though the use of three-dimensional integrated circuits has improved performance and efficiency, the heat generated by the design has become a problem.

“All the heat being generated in this multi-layer stack needs to be removed, otherwise it causes deterioration in performance,” Jain said.

The research team plans to investigate fundamental thermal transport and examine “the thermochemical properties of materials and interfaces in three-dimensional integrated circuit technology,” according to Dereje Agonafer, professor of mechanical and aerospace engineering at UT Arlington and a member of the research team.

The team also plans to examine through-silicon vias (TSVs) as part of their research.

For more information, visit AZ Nano.

By Aliza Becker

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