The researchers demonstrated that a single layer of atoms can disrupt or enhance heat flow across an interface.

The researchers first deposited a single layer of molecules on a quartz surface. Next, through a technique known as transfer-printing, they placed a very thin gold film on top of these molecules. Then they applied a heat pulse to the gold layer and measured how it traveled through the sandwich to the quartz at the bottom.
By adjusting just the composition of the molecules in contact with the gold layer, the group observed a change in heat transfer depending on how strongly the molecule bonded to the gold. They demonstrated that stronger bonding produced a twofold increase in heat flow.

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SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test). More than semiconductors, SEMICON West is also showcase for emerging markets and technologies born from the microelectronics industry, including micro-electromechanical systems (MEMS), photovoltaics (PV), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

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This conference will bring together international researchers and engineers focusing on heat and mass transfer and fluid flow in a variety of applications. The objectives of the meeting are to provide a forum for presentation of state-of-the-art research and opportunities for technical interactions among participants.

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Join us in Montréal Canada to experience a record breaking year for the IEEE International Microwave Symposium (IMS).  Celebrating the 60th anniversary of the Microwave Theory and Techniques Society (MTT-S) and featuring the theme Microwave Without Borders, the IMS2012 will be the centerpiece of Microwave Week June 17-22, 2012.  We have broken many records in the history of the symposium such as the number of paper submissions and the number of advanced bookings by exhibitors. IMS2012 offers technical sessions, interactive forums, plenary and panel sessions, workshops, short courses, industrial exhibits, application seminars, historical exhibits, and a wide array of other technical and social activities. Co-located with IMS2012 are the RFIC symposium (www.rfic2012.org) and the ARFTG conference (www.arftg.org), which comprise the Microwave Week 2012 technical program.  The Microwave Week is the world’s largest gathering of Radio Frequency (RF) and microwave professionals and the most important forum for the latest and most advanced research in the area.

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Chris started work as an Applications Engineer at Philips Semiconductors in 1996, specialising in power MOSFETs. He remained at Philips whilst it became NXP Semiconductors and spends considerable amounts of his working life immersed in questions of a thermal nature. When not sat at his desk watching Profiles windows, he likes nothing better than plodding through muddy fields in the North of England.

As an Application Engineer for a major power semiconductor manufacturer, I spend a great deal of my working life worrying about how to remove heat energy from our MOSFET devices, and hence maintain safe device working temperatures. The majority of our products are surface-mounted, and so use the PCB as their heatsink. Common questions which therefore arise are “How much copper area should I use?”, “What is the influence of PCB layer count?” and “Should I use thermal vias?”. As you can probably imagine, it is impossible to give definitive answers to these questions, as there are so many other factors which contribute to the “thermal performance” of a device or devices mounted on a PCB. However, we do believe that it is possible to give our customers useful information about the relative performance of different PCB configurations, so that they can start to make informed choices about general PCB layout before going into a more detailed design phase.

So far we have produced two lengthy documents on this subject (generated from extensive use of FloTHERM), titled “AN10874 LFPAK MOSFET thermal design guide” and “AN11113 LFPAK MOSFET thermal design guide – Part 2” (will there be a Part 3? who knows…)

Whilst generating the data for Design Guide (part 1) an interesting trend started to emerge, and it is to that subject that I would like to turn. The graph below is reproduced from AN10874, p18, Fig 13.

This graph illustrates the dependence of the temperature of a single device (T_J) on various aspects of PCB configuration. At this point, it helps to see the actual PCB setup:

What we have here is a single MOSFET (in an LFPAK package) mounted on an FR4 PCB with fixed side lengths of 40 x 40mm. Device dissipation is 0.5W and ambient temperature is 20°C. We’re going to have a look at what happens to T_J when we vary the copper dimension “x” for various different PCB stackups i.e.

1. Just the layer 1 copper on its own (pink line on the graph).
2. With a fixed bottom copper layer of 40 x 40mm added (green).
3. As 2., with internal layers (nominal 50% coverage) added (dark blue).
4. As 3., with “thermal vias” added under the device (light blue).

So turning to the pink line (layer 1 only) line first, we can see that when x = 10mm (i.e. a top copper square of side length 10mm) the resulting device temperature (T_J) is 92.1°C or a temperature rise of 72.1°C above ambient (AKA an R_thj-a of 144.2K/W for those who prefer such things). If we now increase “x” to 15mm, we see a dramatic decrease in T_J to 71.2°C. That extra copper area has really helped, reducing T_J by around 22% compared to the original figure! So how about if we increase “x” by another 5mm? Do we see another similar improvement? Well, not really – T_J has dropped from 71.2 to 61.3°C which represents a decrease of 14%. This is still a useful result, but not as dramatic as before. Similarly, increasing “x” by another 5mm (to 25mm) yields a T_J of 55.8°C or a decrease of 9%. So clearly we are seeing the “law of diminishing returns” at work here – adding a modest amount of copper to the PCB layout makes a big difference to T_J, but the improvements become less dramatic as we add even more copper. In fact, you could see this general trend from the shape of the pink line, even without knowing the precise T_J numbers.

So why does the curve have this shape? I would argue that the copper on the periphery plays less of a role in cooling because the heat energy has to pass through the copper nearer the device first in order to reach it. If you like, the copper nearest the device is a thermal resistance which impedes the flow of heat energy to the peripheral copper. We might even deduce that we could reach a point where further increases in “x” result in no further reduction in T_J whatsoever, based on the shape of the graph.

Let’s now look at what happens if we follow the same procedure, but this time with a fixed bottom copper plane added. This is the green “2-layer” curve. Two things stand out clearly:

1. The temperatures for all values of “x” are reduced. This is probably not a surprise.
2. Variation in T_J is less dependent on “x” than for the previous case, but we can still see a “diminishing returns” curve.

For x = 10mm we have a T_J of 63.0°C, with subsequent reductions in T_J of 11%, 4% and 2%. So that extra Layer 1 copper isn’t really buying us much improvement at all.

Now we’ll add some internal copper planes (4-layer curve in dark blue). As might be expected, the temperatures have come down even further, and the shape of the curve indicates even less dependence of T_J on top copper area. In fact, the percentage reduction in T_J when going from x = 10mm to x = 25mm is only around 7.5%.

Finally, we added a 5×4 pattern of 0.8mm diameter vias under the device, which would also have the effect of electrically connecting the top copper plane to the bottom copper plane. The results are shown by the light blue “4-layer (5×4 vias)” line. Once more we have an overall reduction in T_J (although not dramatically so), and T_J has become pretty much independent of “x”. What we can also see is that adding progressively more copper to the board (i.e. layers and vias) has also yielded “diminishing returns”. In fact, if we model a PCB made of pure copper (an impractical configuration, but one which we are quite able to investigate in simulation) then the improvement is little beyond what we already see for the “4-layer (5×4 vias)” line.

I mentioned at the beginning that the purpose of this exercise was to give the PCB designer an idea of the relative performance of different PCB configurations. The trends we have seen here can therefore be summarised as:

1. The presence of multiple PCB layers diminishes the importance of top copper area in device cooling.
2. If you’re designing a multi-layer board (and who isn’t these days?) then there is probably no point expending large areas of top copper in trying to reduce device temperatures. You can safely reserve this board area for other purposes.
3. Thermal vias can also help, if the circuit topology allows for them.

For much more detail on this subject, including the behaviour of multiple devices on a PCB and the influence of an enclosure around the PCB, the reader is urged to follow links to AN10874 and AN11113.

NFPA 70E is the standard for electrical safety in the workplace, and explains in detail how to prevent electrical hazards. In this paper, Mersen identifies and explains some of the key changes to NFPA 70E for 2012.

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Rehm Thermal Systems is the leading soldering supplier to the global automotive electronics industry, and has operated directly in North America for over a decade.

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Northrop Grumman’s AFT technology improves the air cooling of advanced electronic modules through the use of a compact core style heat exchanger design that significantly increases the cooling efficiency of removable electronic modules such as VPX (VITA 46/48) cards.

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Germanium grown epitaxially on micrometre-sized silicon pillars forms perfect crystals free of defects. The resulting Ge/Si “virtual substrate” is lighter and tougher than a free-standing Ge substrate and clears a path towards high-resolution CMOS X-ray detectors and high-efficiency multi-junction solar cells for both space and terrestrial applications.

Micrometre-scale layers of pure Ge are attractive for infra-red photodetectors, the final layer of triple-junction solar cells, or as “virtual substrates” for the deposition of GaAs-based layers. Increasing the Ge thickness still further (to several tens of micrometres) would enable the realisation of X-ray and particle detectors which are more efficient than their existing Si-based counterparts. The increased efficiency coupled with the good compatibility between Ge and Si leads to the final goal of a pixel detector in which the Ge absorbs the photons or particles and the resulting signals are handled by Si CMOS readout electronics.

The growth technique of low-energy plasma-enhanced chemical vapour deposition (LEPECVD) [3] has led to the efficient and fast deposition of such layers, but, once the Ge layer is more than a few micrometres thick, the thermal contraction during the cooling of the substrate back to room temperature after growth causes bending of the substrate and cracking of the Ge layer.

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Tilman Esslinger, Professor at the Institute of Quantum Electronics, ETH Zurich, and his team loaded ultracold potassium atoms into a special lattice structure made of laser light: the researchers used a set of orthogonal and precisely positioned laser beams to create a variety of two-dimensional light field geometries, including the honeycomb structure of graphene.

In the experiment they cooled several hundred thousand potassium atoms inside a vacuum chamber to temperatures just above absolute zero, thereby bringing the atoms to rest. Then, they place the optical lattice over the cloud of atoms.

Once trapped in the optical lattice, the potassium atoms behave like electrons in the crystal structure of graphene. By accelerating the atoms with a magnetic field gradient, the researchers could identify Dirac points in the optical lattice. Near a Dirac point the atoms behave like massless particles — just as the electrons in graphene — and they can move from the valance to the conduction band since the band gap vanishes.

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