Introduction and Summary
In today’s competitive environment, the electronics industry is focusing onbusiness process re-engineering or product improvements with emphasis ondevelopment and manufacturing intervals and costs, warranty costs, fieldreliability, and customer maintenance costs. Some of the improvement methodsused are cross-functional teams, concurrent engineering, simulation, six-sigmaand robust design analysis, environmental stress testing (EST), and many others.This paper describes the EST method and its implementation in development andmanufacturing processes.
EST is an effective method for improving product reliability. Electronicproducts typically have potential latent defects or weaknesses, which can causefailures during field operation. EST is the application of stress tests atlevels beyond design limits, to turn potential latent defects into failures;failure mode analysis (FMA) is used to identify the root causes, and takecorrective action. EST is used during development to identify potential designmargin weaknesses. In manufacturing, EST is used to identify potential processand component latent defects, or to screen for specific failure mechanisms. Theprimary objective of EST is to identify and correct any potential latent defectsquickly, while minimizing the overall product cost. Development andmanufacturing groups, suppliers, and other equipment manufacturers (OEMs) mayuse and benefit from EST.
Background – Examples
In the 1960s, space program suppliers used environmental stress screening(ESS). Production volume was small, hence, there was no effort to perform FMAand identify the root causes. Stress tests were applied at levels that simulatedfield operation and did not exceed the design limits.
The objective of ESS was to screen the bad from the good product. In the1970s, the ESS approach was adopted by the military defense industry. Militarysuppliers were required to perform ESS on 100% of production. Hence, ESS wasexpensive. For details about ESS, see reference .
In the 1980s, major electronic companies improved ESS and created the ESTmethod. This method is used for improvements during development andmanufacturing. EST incorporates the use of FMA and corrective action. Theobjective is to produce a robust and reliable product with lower overall cost.Commercial companies such as AT&T, Boeing, Hewlett Packard and IBM, havebeen using EST to improve their design and manufacturing processes, reducewarranty repairs, improve field reliability, and achieve significant costsavings. Examples about EST are presented in references [2-6].
An EST program includes processes for development and manufacturing,suppliers, OEMs, and FMA and corrective action. EST processes are based oncustomer, market and internal requirements. An FMA and corrective action processis needed for a timely identification of the failure mechanism(s) andcorrection. Emphasis is placed on integrating the EST processes in thedevelopment and manufacturing processes, and eliminating any duplication oftests.
The success of an EST program implementation depends heavily on management’scommitment and support. If that commitment exists, the Manager will allocate theresources. A cross-functional team approach may be used. An EST team is formedwith representatives from development, manufacturing, component, QC/QA, andfield repair groups. A team leader is responsible for leading and managing theEST program. An FMA coordinator oversees the FMA activities. The team must beinnovative, persistent, and willing to try novel methods. A change control (CC)system is recommended to document all the verified problems discovered due toEST. A modification request (MR) should be entered in the CC system for each ESTfailure. The use of such a system provides the visibility needed for the ESTfailures and the timely corrective action.
Certainly, every EST team will discover problems. In either case, decisionsmust be made about stopping production, problem correction and customershipments. The team should thoroughly analyze each situation separately.Emphasis is placed on the magnitude of the defect, timely problem correction,warranty costs, and customer shipments. Based on results, the Manager can make adecision that will not jeopardize customer relationships and product sales.
Stress Tests and Conditions
Typical stress tests are, temperature, voltage and clock variation,temperature cycling, power cycling, humidity, thermal shock, random vibration,electro-static discharge (ESD), EMI susceptibility, and product specific tests.Each stress test has the ability to stimulate different latent defects. Forexample, temperature is used to detect design margin flaws and componentdefects; temperature cycling is used to detect interconnection and packagingdefects. Stress tests should be combined and applied simultaneously, while theproduct is powered and monitored.
EST may be applied on as few as 3-5 models. Stress levels are increased instep increments and testing is continued until the product can operate at levelsat least 20-30% higher than the required limits. For example, if the productmust operate up to 50°C, it should be able to operate at least at 60°C.If the product fails, it should be repaired and testing continued until mostmodels can operate at the desired stress levels. Significant drawbacks are theavailability of models, the ability to diagnose problems at high stress levels,and FMA support by suppliers.
When EST is used on production units to screen a specific failure mechanism,the stress tests should be applied above the required customer limits, but belowthe operating limits. A proof of screen should be developed to specify theappropriate stress levels for production units.
EST may be applied on design models. The objective is to identify andcorrect any potential design margin weaknesses prior to initial production.Stress tests are selected based on customer requirements, component technologiesused, and field reliability of similar products. Field repair, FMA and failuremechanism data provide excellent input to the selection of the stress tests. Ata minimum, the EST process should include the stress tests listed above.
Drawbacks of using EST on design models are incomplete hardware andsoftware, unavailable system tests and diagnostics, tight development scheduleswith no allowance for a 2nd iteration, and limited resources. The EST team needsto work with development groups to implement as much of the EST process aspossible at the card, sub-system and system level. Any incomplete stress testsshould be included in manufacturing EST.
A manufacturing EST process complements the development EST process. Thisprocess should be used on initial production models to identify and correct anypotential manufacturing process and component defects. This process may also beused periodically on a few production units to thoroughly check for any shiftsin the design margins, manufacturing processes, or component quality. Such unitsshould not be shipped, since these stress tests may be destructive. EST andfield failure mechanism data is used to select the stress tests.
Initial production should be subjected to EST. As sufficient data indicatesthat no potential failure mechanisms are present, perform EST on a sample basis(sampling EST) or no EST may be initiated. Sampling EST requires a samplingscheme and a decision process to switch to a 100% production EST or no EST. Thedecision process is based on the factory and any available field data. Thestress tests are selected based on the observed failure mechanisms and performedat non-destructive levels. It is essential that when EST is used on productionunits, the stress levels are severe enough to precipitate the latent defects,but without causing damage to good units.
Manufacturing EST requires a commitment for FMA. If this effort is not supported, EST becomes a 100% production screen which is usually expensive andunnecessary for mature products. If 100% production EST is a customerrequirement, the factory and field data should be used to demonstrate thebenefits of sampling EST and the potential cost savings to the customer.
Suppliers and OEMs
An EST program should address components, modules, cards, and sub-systemspurchased from suppliers and OEMs. Minimum requirements and design limits shouldbe specified for every part purchased based on the product requirements. ESTshould be incorporated in the suppliers’ processes. At a minimum, suppliersshould use EST to demonstrate that their product meets or exceeds the specifiedlimits. For example, if a card must pass an 85°C temperature test, allcomponent and modules used on that card must meet this requirement. Suchspecifications should be included in the supplier contract agreement.
Failure Mode Analysis
An integral part of an EST program is a strong FMA effort. Every EST failureshould be subjected to FMA down to the lowest actionable level, to identify anyfailure mechanisms. Corrective action and any improvements should be implementedand verified. The impact of timely improvements is enormous for large volumeproducts. Attention should be paid to soft failures, i.e., units that fail at acertain stress level but recover at a lower stress level. Such failures aredifficult to diagnose and time consuming. In addition, it is a challenge to getsuppliers to perform FMA on units that have failed above their design limits. Afailure reporting, analysis, and corrective action system (FRACAS) isrecommended to keep track and save all the data. Similarly, FMA should beperformed on manufacturing defects and field indicted units to identify relatedfailure mechanisms. Such information is essential for the continuous improvementof EST.
Data Collection and Analysis
EST data should be collected and analyzed. This includes failure, test,repair and FMA data, failure mechanism(s), and any corrective action. Regardingmanufacturing data, emphasis should be placed on card and system test defects,components indicted and their associated failure mechanisms. For field data,emphasis should be placed on field failures, components indicted and theirassociated failure mechanisms.
Failure mechanisms associated with EST, manufacturing, and field defectsshould be compared and appropriate corrective action taken. For example, iffield and EST failure mechanisms are the same, the stress tests and conditionsmust be modified, so that these latent defects are caught during manufacturingEST and not during field operation. The data may also be used to comparedifferent EST programs.
EST costs should be evaluated and compared with potential cost savings. Itis assumed that products with latent defects fail during EST and are not shippedto customers. Furthermore, if EST is not performed, such products will failduring field operation. Typically, EST costs include cost of models, resources,facilities, floor space, repair of EST defects, and FMA support. Cost savingsare due to reduced manufacturing, handling and shipping, warranty and repaircosts. In addition, the impact on customer maintenance costs should beconsidered.
A spreadsheet program may be used to perform what-if analyses and toevaluate the full impact of EST prior to making any decisions. Factors, such as production volume and product cost, plus warranty repair policy should beconsidered. For example, if low cost circuit cards are not repaired but replacedwith a working unit, EST will not generate any cost savings due to a reductionin warranty repairs.
Conclusions – Next Step
EST is an excellent method to improve development and manufacturingprocesses and costs, field reliability, and customer maintenance costs. Across-functional team is recommended to achieve implementation efficiencies.Strong FMA effort is also required to achieve the full benefits of EST. Finally,the success of EST is solely rested on management’s commitment and support.Future work includes the integration of simulation, robust design or six sigmaanalysis and EST.
 Environmental Stress Screening Guidelines forAssemblies, Institute of Environmental Sciences, March 1990.
 G.K. Hobbs, HALT and HASS, Course Notes, October 1993.
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 R.W. Deppe and E.O. Minor, Reliability Enhancement Testing, 1994 Proceedings Annual Reliability and Maintainability Symposium, January 1994,pp. 91-98.
 T.P. Parker, A Study of Failures Identified During Board LevelEnvironmental Stress Testing, IEEE Transactions onComponents, Hybrids, and Manufacturing Technology,Vol. 15, No. 6, December 1992, pp.1086-1092.
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