Heat dissipation of active devices has become one of the limiting factors in further miniaturization. While component manufacturers succeed in decreasing the overall thermal resistance of their packages, the thermal interface resistance to the board becomes the next limiting factor. Therefore, understanding interface and contact resistances becomes increasingly important for … [Read more...]
Archives for September 2000
Determining the junction temperature in a semiconductor package, part IV – localized heat generation on the die
In the standard thermal test environment, thermal test chips are designed to dissipate the applied power uniformly over most of the die surface. However, in many situations of practical interest, the power is dissipated over a localized area of the die. This column provides calculation methods to deal with the latter situation. Figure 1 illustrates the situation of interest … [Read more...]