By: Wen Yueh, Khondker Z. Ahmed, and Saibal Mukhopadhyay
School of ECE, Georgia Institute of Technology
Thermal test chips with integrated thin-film heaters via post-processing are often used as the test structure to evaluate thermal integrity of the packages and cooling solutions . In advanced silicon technologies (sub-45nm nodes), the chip’s thermal design point (TDP) is often a determining factor for the performance and energy-efficiency in multi-core microprocessors . However, time-varying workloads in processors can lead to time-varying temperature, and impact the integrated circuit (IC’s) performance and power. Therefore, it is crucial for the future test vehicles to characterize the interactions among application dependent power patterns, chip/package’s thermal properties, cooling technologies, and circuit functionalities. The thermal test-chip should be designed and fabricated in the standard silicon process and may be embedded in the packaging and cooling technology candidates. The chip’s programmability to emulate the time-varying power patterns of real applications is required for on-chip characterization of spatiotemporal temperature variations and its impact on the circuit’s performance, power, and reliability; instead of only ensuring thermal integrity at the peak power density. An all-silicon structure with on-line programmable power and on-chip characterization sensors integrates well with the IC design flow and is a preferable solution for holistic power, temperature, and circuit analysis. This article introduces a thermal test structure, referred to as the field-programmable thermal emulator (FPTE), to achieve this goal.
Figure 1 – A conceptual diagram of a field programmable thermal emulator (FPTE) integrated into an instrumentation board
for thermal characterization.
Field-Programmable Thermal Emulator
Parallel to the field-programmable gate array (FPGA) in functional emulation, FPTE emulates the thermal field using programmable on-die CMOS based heater array and on-die sensors for temperature and circuit properties. On die programmable heaters are controlled with the integrated registers, to emulate time-varying power patterns and generate time-varying temperature pattern. Multiple digitally programmable FPTE cores are integrated on-chip to characterize the thermal effects in multi-core processing including core-to-core thermal coupling. The FPTE cores are augmented with the analog temperature sensors to record the temperature patterns and digital circuits to characterize the changes in the electrical characteristics. The conceptual diagram in Figure 1 shows an FPTE chip integrated into a board. An on-board microcontroller can be used to drive test applications and record the sensor outputs for automated measurement and characterization. The cartoon highlights an on-line field-programmable thermal characterization framework on board.
An Example FPTE Test-Chip
A simplified FPTE test-chip to demonstrate the design concept is presented in Figure 2 . The die photo of the designed test chip shows five digitally controllable heaters, five digital sensors, and serial-to-parallel-interface (SPI) registers. The on-chip SPI programs heater registers for heating and records data from the sensor registers . The FPTE hotspots at the corners are 600 μm apart horizontally and 750 μm apart vertically. An additional hotspot is placed at the center of the chip. The core of the FPTE block is the programmable CMOS heater that is made of an n-well resistor to generate heat within the silicon at the junction. An NMOS transistor with binary (‘high’ and ‘low’) states controls the current through the resistor. The resistor bank is arranged in groups of resistors with maximum equivalent resistance as 250 ohms. Each resistor bank is formed by 4 x 4 sub-bank tiles. Each tile is 60 μm x 50 μm in size and shares the control signal to improve intra-bank uniformity in generated heat. Each resistor bank is designed to generate 16 current levels with maximum 165 mA at 3.3 V, resulting in the maximum instantaneous heater power of 544.5 mW at the granularity of 34 mW. The total area of the heater hotspot is 250 μm x 150 μm i.e. 0.0375 mm2. Each FPTE cell dissipates ~9 uW of standby power. The maximum power of each bank may be controlled using an external voltage source or on-chip voltage regulators. The internal registers can then tune the individual heater output at a fine-grain level. The latch based registers for heaters and sensors have a footprint of 250μm x 150μm. The fill-factor for a single FPTE is designed to be 50% and the density may further improve if SRAM is used for the register cells. The heater drivers are designed to sink the full swing current with rise/fall time at ~20 ns.
The conventional bipolar junction transistor (BJT) based analog temperature sensors are included in the design. The outputs of the analog sensors are quantized using external analog-to-digital converters (ADCs). To characterize the interaction between delay and temperature patterns, digital ring oscillators (performance sensors) are integrated within the FPTE blocks. The delay-based sensors store temperature history in 8-bit word and the first-in-first-out (FIFO) buffer holds up to 16 entries in the register.
The test chip was designed and fabricated in a 130 nm CMOS process. Figure 3a shows the measurement set up to verify the operation of the FPTE. A program stored in the microcontroller controlled the heaters and obtained the sensor readings. The automated measurement demonstrates the feasibility of a high-speed test and characterization using the platform. Figure 3b shows the experimental result where time-varying arbitrary power pattern is generated in the chip and recording from the delay based digital temperature sensors. The test case demonstrated programmable time-varying power pattern in the heaters. The FPTE sensors identified the coupled time-varying temperature. The measured reading from the delay sensors showed that due to the power-thermal-performance correlation, the power dissipation in the chip modulates a circuit’s performance. The arbitrary power profile may be driven by realistic power trace from measurements of current processor or from architecture simulators for predictive architectures. The measurements can be repeated for different packaging conditions as well as using different external cooling technologies to understand their transient properties.
The FPTE uses on-chip digital heaters and sensors to emulate time-varying power patterns on-chip, generate the corresponding spatiotemporally varying temperature pattern, and characterize the resulting variations in circuit properties. The application domains of FPTE include a thermal test-vehicle as well as an on-line thermal test-structure.
Figure 2 – An example implementation of an FPTE design and corresponding test-chip in 130nm CMOS .
Figure 3 – A snapshot of the measurement environment and sample results.
As a thermal test-vehicle, FPTE has the advantage over existing thin-film heater based approaches due to its compatibility with standard CMOS process, ability to generate controllable and time-varying power patterns, and directly characterize the effect of temperature patterns on device characteristics. Application of FPTE as a test-vehicle to evaluate advanced microfluidic cooling has been presented by Wan et. al. . In the experiment, the silicon interposer with etched micro pin-fins was attached directly with the FPTE die. The FPTE was used to directly characterize the effect of fluidic cooling on the circuit properties, for example, the trade-off between flow rate (cooling power) and the potential leakage power saving.
As an on-chip test structure, an FPTE block may be embedded within a microprocessor core with minimal overhead, because of its low standby power and small area. A built-in self-test routine may apply test power patterns to validate/ensure thermal fidelity of a specific packaged IC considering process variations as well as the time-dependent degradation in the thermal properties . The thermal characteristics of packaged chips may be extracted in the form of frequency-domain thermal filters as presented by Kung et. al. . The extracted filter was used to accurately predict the transient temperature pattern for spatiotemporally varying power patterns. The filter also estimate power pattern from measured temperature accurately, which implies FPTE can facilitate on-line real-time temperature/power prediction in an IC.
Plans for Future Development
The FPTE test-chip presented in Figure 2 can be extended to enrich the characterization framework. Increasing the density of the heater cells will help emulate higher hotspot density. Currently, the design is capable of programming arbitrary power pattern over time; a potential extension is to improve the spatial controllability to generate arbitrary power pattern in space to enable true spatiotemporal controllability. The presented design depends on externally available power pattern to emulate a workload. In the future, it will be important to consider built-in ‘power pattern generators’ that consists of fundamental logic and memory blocks with controllable activity patterns. Finally, it will be interesting to pursue embedding of FPTE as an Intellectual Property (IP) block within a processor design.
In integrated circuits, especially in high-performance microprocessors, the run-time thermal management is critical to ensure performance, power, and reliability of the IC. A CMOS based design is effective to emulate the thermal effects of any time-varying power patterns utilizing standard digital I/Os. The CMOS-only test vehicles, such as the FPTE, reduce test cost, improve testability, and extend observability. The FPTE structure presented in this article is an important step towards this direction and opens opportunities for future studies.
This work is supported in part by Semiconductor Research Corp (#2084.001) and Sandia National Laboratory.
- B. Siegal and J. Galloway, “Thermal Test Chip Design and Performance Considerations,” in IEEE SEMI-THERM 2008, pp. 59-62, March 16-20, March 2008.
- J. Kong, S. W. Chung, and K. Skadron., “Recent Thermal Management Techniques for Microprocessors,” ACM Computing Surveys vol. 44(3), pp. 13-42. June 2012.
- W. Yueh, K. Z. Ahmed, and S. Mukhopadhyay, “Field Programmable Thermal Emulator (FPTE): An All-silicon Test Structure for Thermal Characterization of Integrated Circuits,” in IEEE SEMI-THERM 2014, pp. 66-71, March 9-13, 2014.
- Z. Wan, W. Yueh, Y. Joshi, and S. Mukhopadhyay, “Enhancement in CMOS Chip Performance through Microfluidic Cooling ,” in THERMINIC 2014, pp. 24-26, September 2014.
- M. Cho, W. Song, S. Yalamanchili, and S. Mukhopadhyay, “Thermal system identification (TSI): A Methodology for Post-silicon Characterization and Prediction of the Transient Thermal Field in Multicore Chips,” in IEEE SEMI-THERM 2012, pp.118-124, March 18-22 , 2012.
- J. Kung, W. Yueh, S. Yalamanchili, and S. Mukhopadhyay, “Post-silicon Estimation of Spatiotemporal Temperature Variations Using MIMO Thermal Filters,” IEEE Trans. Compon. Packag. Manuf. Technol. 2014, in press.